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| ? 2002 microchip technology inc. ds21734a-page 1 m TC654/tc655 features ? temperature proportional fan speed for reduced acoustic noise and longer fan life ? fansense? protects against fan failure and eliminates the need for 3-wire fans ? over temperature detection (tc655) ? efficient pwm fan drive ? provides rpm data ? 2-wire smbus?-compatible interface ? supports any fan voltage ? software controlled shutdown mode for "green" systems ? supports low cost ntc/ptc thermistors ? space saving 10-pin msop package ? temperature range: -40c to +85oc applications ? personal computers & servers ? lcd projectors ? datacom & telecom equipment ? fan trays ? file servers ? workstations ? general purpose fan speed control package type description the TC654 and tc655 are pwm mode fan speed con- trollers with fansense technology for use with brush- less dc fans. these devices implement temperature proportional fan speed control which lowers acoustic fan noise and increases fan life. the voltage at v in (pin 1) represents temperature and is typically pro- vided by an external thermistor or voltage output tem- perature sensor. the pwm output (v out ) is adjusted between 30% and 100%, based on the voltage at v in . the pwm duty cycle can also be programmed via smbus to allow fan speed control without the need for an external thermistor. if v in is not connected, the TC654/tc655 will start driving the fan at a default duty cycle of 39.33%. see section 4.3, "fan startup", for more details. in normal fan operation, pulse trains are present at sense1 (pin 8) and sense2 (pin 7). the TC654/ tc655 use these pulses to calculate the fan revolu- tions per minute (rpm). the fan rpm data is used to detect a worn out, stalled, open or unconnected fan. an rpm level below the user-programmable threshold causes the TC654/tc655 to assert a logic low alert signal (fault ). the default threshold value is 500 rpm. also, if this condition occurs, f1f (bit 0<0>) or f2f (bit 1<0>) in the status register will also be set to a ? 1 ?. an over-temperature condition is indicated when the voltage at v in exceeds 2.6 v (typical). the TC654/ tc655 devices indicate this by setting otf(bit 5 TC654/tc655 ds21734a-page 2 ? 2002 microchip technology inc. functional block diagram v otf 50 k ? otf v min TC654/tc655 sense1 fault v out v dd gnd sda sclk c f v in ? + + ? clock generator serial port interface control logic start-up timer missing pulse detect 100 mv (typ.) + ? 50 k ? sense2 100 mv (typ.) + ? ? + note: otf condition applies for the tc655 device only. note ? 2002 microchip technology inc. ds21734a-page 3 TC654/tc655 1.0 electrical characteristics absolute maximum ratings * v dd ..................................................................................6.5 v input voltages .................................... -0.3 v to (v dd + 0.3 v) output voltages ................................. -0.3 v to (v dd + 0.3 v) storage temperature .....................................-65c to +150c ambient temp. with power applied ................-40c to +125c maximum junction temperature, t j ............................. 150c esd protection on all pins .................................................. 4kv * notice: stresses above those listed under ?maximum rat- ings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. expo- sure to maximum rating conditions for extended periods may affect device reliability. pin function table name function v in analog input c f analog output sclk serial clock input sda serial data in/out (open drain) gnd ground fault digital (open drain) output sense2 analog input sense1 analog input v out digital output v dd power supply input electrical specifications electrical characteristics: unless otherwise noted, all limits are specified for v dd = 3.0 v to 5.5 v, -40c TC654/tc655 ds21734a-page 4 ? 2002 microchip technology inc. temperature specifications timing specifications 2-wire serial bus interface logic input high v ih 2.1 ? ? v note 2 logic input low v il ??0.8v logic output low v ol ??0.4vi ol = 3 ma input capacitance sda, sclk c in ?10 15pf note 1 i/o leakage current i leak -1.0 ? +1.0 a sda output low current i olsda 6??mav ol = 0.6 v electrical characteristics: unless otherwise noted, all parameters apply at v dd = 3.0 v to 5.5 v parameters symbol min typ max units conditions temperature ranges specified temperature range t a -40 ? +85 c operating temperature range t a -40 ? +125 c storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 10 pin msop ja ?113?c/w electrical characteristics: unless otherwise noted, all limits are specified for v dd = 3.0 v to 5.5 v, -40c ? 2002 microchip technology inc. ds21734a-page 5 TC654/tc655 figure 1-1: bus timing data. t su(start) t h(start) t su-data t su(stop) t idle a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave e = slave pulls sda line low a b cd e fg h i j kl m f = acknowledge bit clocked into master g = msb of data clocked into slave h = lsb of data clocked into slave i = slave pulls sda line low j = acknowledge clocked into master k = acknowledge clock pulse l = stop condition, data executed by slave m = new start condition t low t high sclk sda t h-data smbus write timing diagram t su(start) t h(start) t su-data t su(stop) t idle a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave a b cdef g h ij k e = slave pulls sda line low f = acknowledge bit clocked into master g = msb of data clocked into master h = lsb of data clocked into master t low t high i = acknowledge clock pulse j = stop condition k = new start condition sclk sda smbus read timing diagram e TC654/tc655 ds21734a-page 6 ? 2002 microchip technology inc. 2.0 typical performance curves figure 2-1: i dd vs. temperature. figure 2-2: i dd shutdown vs. temperature. figure 2-3: pwm, source current vs. temperature. figure 2-4: pwm, sink current vs. temperature. figure 2-5: fault v ol vs. temperature. figure 2-6: pwm frequency vs. temperature. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 130 135 140 145 150 155 160 165 170 175 180 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) i dd (a) v dd = 5.5 v v dd = 3.0 v pins 7,8, and 9 open 1.000 2.000 3.000 4.000 5.000 6.000 7.000 8.000 9.000 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (oc) shutdown i dd (a) v dd = 3.0 v v dd = 5.5 v 5 10 15 20 25 30 35 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) source current (ma) v dd = 5.5 v v dd = 5.0 v v dd = 4.0 v v dd = 3.0 v v oh = 0.8v dd 2 4 6 8 10 12 14 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) sink current (ma) v dd = 5.5 v v dd = 5.0 v v dd = 4.0 v v dd = 3.0 v v ol = 0.1 v dd 15 20 25 30 35 40 45 50 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (oc) fault v ol (mv) i ol = 2.5 ma v dd = 5.5 v v dd = 5.0 v v dd = 4.0 v v dd = 3.0 v 27 28 29 30 31 32 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (oc) pwm frequency (hz) v dd = 5.5 v v dd = 3.0 v c f = 1.0 f ? 2002 microchip technology inc. ds21734a-page 7 TC654/tc655 figure 2-7: sda i ol vs. temperature. figure 2-8: v cmax vs. temperature. figure 2-9: v cmin vs. temperature. figure 2-10: rpm %error vs. temperature. figure 2-11: sense threshold (v thsense ) hysteresis vs. temperature. figure 2-12: sda, sclk hysteresis vs. temperature. 20 25 30 35 40 45 50 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (oc) sda i ol (ma) v ol = 0.4 v v dd = 5.5 v v dd = 5.0 v v dd = 4.0 v v dd = 3.0 v 2.575 2.580 2.585 2.590 2.595 2.600 2.605 2.610 2.615 2.620 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (oc) v cmax (v) v dd = 3.0 v v dd = 4.0 v v dd = 5.0 v v dd = 5.5 v 1.180 1.185 1.190 1.195 1.200 1.205 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (oc) v cmin (v) v dd = 3.0 v v dd = 5.0 v v dd = 5.5 v v dd = 4.0 v 0 1 2 3 4 5 6 7 8 9 10 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (oc) rpm error (%) v dd = 3.0 v v dd = 5.5 v v dd = 5.0 v c f = 1.0 f 20 25 30 35 40 45 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (oc) v thsense hysteresis (mv) v dd = 3.0v v dd = 5.5v 80 90 100 110 120 130 140 150 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (oc) sda & sclk hysteresis (mv) v dd = 3.0 v v dd = 5.0 v TC654/tc655 ds21734a-page 8 ? 2002 microchip technology inc. 3.0 pin functions the descriptions of the pins are listed in table 3-1. table 3-1: pin function table 3.1 analog input (v in ) a voltage range of 1.62 v to 2.6 v (typical) on this pin drives an active duty-cycle of 30% to 100% on the v out pin. 3.2 analog output (c f ) positive terminal for the pwm ramp generator timing capacitor. the recommended c f is 1 f for 30 hz pwm operation. 3.3 smbus serial clock input (sclk) clocks data into and out of the TC654/tc655. see section 5.0 for more information on the serial interface. 3.4 serial data (bi-directional) (sda) serial data is transferred on the smbus in both direc- tions using this pin. see section 5.0 for more informa- tion on the serial interface. 3.5 digital (open drain) output (fault ) when the fan?s rpm falls below the user-set rpm threshold (or otf occurs with tc655), a logic low sig- nal is asserted. 3.6 analog input (sense2) fan current pulses are detected at this pin. these pulses are counted and used in the calculation of the fan2 rpm. 3.7 analog input (sense1) fan current pulses are detected at this pin. these pulses are counted and used in the calculation of the fan1 rpm. 3.8 digital output (v out ) this active high complimentary output drives the base of an external transistor or the gate of a mosfet. 3.9 power supply input (v dd ) the v dd pin with respect to gnd provides power to the device. this bias supply voltage may be independent of the fan power supply. name function v in analog input c f analog output sclk serial clock input sda serial data in/out (open drain) gnd ground fault digital (open drain) output sense2 analog input sense1 analog input v out digital output v dd power supply input ? 2002 microchip technology inc. ds21734a-page 9 TC654/tc655 4.0 device operation the TC654 and tc655 devices allow you to control, monitor and communicate (via smbus) fan speed for 2- wire and 3-wire dc brushless fans. by pulse width modulating (pwm) the voltage across the fan, the TC654/tc655 controls fan speed according to the sys- tem temperature.the goal of temperature proportional fan speed control is to reduce fan power consumption, increase fan life and reduce system acoustic noise. with the TC654 and tc655 devices, fan speed can be controlled by the analog input v in or the smbus inter- face, allowing for high system flexibility. the TC654 and tc655 also measure and monitor fan revolutions per minute (rpm). a fan?s speed (rpm) is a measure of its health. as a fan?s bearings wear out, the fan slows down and eventually stops (locked rotor). by monitoring the fan?s rpm level, the TC654/tc655 devices can detect open, shorted, unconnected and locked rotor fan conditions. the fan speed threshold can be set to provide a predictive fan failure feature. this feature can be used to give a system warning and, in many cases, help to avoid a system thermal shut- down condition. the fan rpm data and threshold reg- isters are available over the smbus interface which allows for complete system control. the TC654/tc655 devices are identical in every aspect except for how they indicate an over-tempera- ture condition. when v in voltage exceeds 2.6 v (typi- cal), both devices will set otf (bit 5 TC654/tc655 ds21734a-page 10 ? 2002 microchip technology inc. 4.1 fan speed control methods the speed of a dc brushless fan is proportional to the voltage across it. for example, if a fan?s rating is 5000 rpm at 12 v, it?s speed would be 2500 rpm at 6 v. this, of course, will not be exact, but should be close. there are two main methods for fan speed control. the first is pulse width modulation (pwm) and the second is linear. using either method the total system power requirement to run the fan is equal. the difference between the two methods is where the power is consumed. the following example compares the two methods for a 12 v, 120 ma fan running at 50% speed. with 6 v applied across the fan, the fan draws an average cur- rent of 68 ma. using a linear control method, there is 6v across the fan and 6v across the drive element. with 6 v and 68 ma, the drive element is dissipating 410 mw of power. using the pwm approach, the fan is modulated at a 50% duty cycle, with most of the 12 v being dropped across the fan. with 50% duty cycle, the fan draws an rms current of 110 ma and an average current of 72 ma. using a mosfet with a 1 ? rds (on) (a fairly typical value for this low current) the power dis- sipation in the drive element would be: 12 mw (irms 2 * rds (on) ). using a standard 2n2222a npn transistor (assuming a vce-sat of 0.8 v), the power dissipation would be 58 mw (iavg* vce-sat). the pwm approach to fan speed control causes much less power dissipation in the drive element. this allows smaller devices to be used and will not require any spe- cial heatsinking to get rid of the power being dissipated in the package. the other advantage to the pwm approach is that the voltage being applied to the fan is always near 12 v. this eliminates any concern about not supplying a high enough voltage to run the internal fan components which is very relevant in linear fan speed control. 4.2 pwm fan speed control the TC654 and tc655 devices implement pwm fan speed control by varying the duty cycle of a fixed fre- quency pulse train. the duty cycle of a waveform is the on time divided by the total period of the pulse. for example, given a 100 hz waveform (10 msec.) with an on time of 5.0 msec, the duty cycle of this waveform is 50% (5.0 msec/10.0 msec). an example of this is illustrated in figure 4-2. figure 4-2: duty cycle of a pwm waveform. the TC654 and tc655 generate a pulse train with a typical frequency of 30 hz (c f = 1 f). the duty cycle can be varied from 30% to 100%. the pulse train gen- erated by the TC654/tc655 devices drives the gate of an external n-channel mosfet or the base of an npn transistor (figure 4-3). see section 7.5 for more information on output drive device selection. figure 4-3: pwm fan drive. by modulating the voltage applied to the gate of the mosfet qdrive, the voltage applied to the fan is also modulated. when the v out pulse is high, the gate of the mosfet is turned on, pulling the voltage at the drain of qdrive to 0 v. this places the full 12 v across the fan for the ton period of the pulse. when the duty cycle of the drive pulse is 100% (full on, ton = t), the fan will run at full speed. as the duty cycle is decreased (pulse on time ?ton? is lowered), the fan will slow down proportionally. with the TC654 and tc655 devices, the duty cycle can be controlled through the analog input pin (v in ) or through the smbus interface by using the duty-cycle register. see section 4.5 for more details on duty cycle control. t to n to ff t = period t = 1/f f = frequency d = duty cycle d = ton / t TC654/ tc655 fan 12 v qdrive v dd gnd v out g d s ? 2002 microchip technology inc. ds21734a-page 11 TC654/tc655 4.3 fan startup often overlooked in fan speed control is the actual startup control period. when starting a fan from a non- operating condition (fan speed is zero rpm), the desired pwm duty cycle or average fan voltage can not be applied immediately. since the fan is at a rest posi- tion, the fan?s inertia must be overcome to get it started. the best way to accomplish this is to apply the full rated voltage to the fan for one second. this will ensure that in all operating environments, the fan will start and operate properly. the TC654 and tc655 devices implement this fan con- trol feature without any user programming. during a power up or release from shutdown condition, the TC654 and tc655 devices force the v out output to a 100% duty cycle, turning the fan full on for one second (c f = 1 f). once the one second period is over, the TC654/tc655 devices will look to see if smbus or v in control has been selected in the configuration register (dutyc bit 5<0>). based on this register, the device will choose which input will control the v out duty cycle. duty cycle control based on v in is the default state. if v in control is selected and the v in pin is open (nothing is connected to the v in pin), then the TC654/tc655 will default to a duty cycle of 39.33%. this sequence is shown in figure 4-4. this integrated one second star- tup feature will ensure the fan starts up every time. figure 4-4: power-up flow chart. 4.4 pwm drive frequency (c f ) as previously discussed, the TC654 and tc655 devices operate with a fixed pwm frequency. the fre- quency of the pwm drive output (v out ) is set by a capacitor at the c f pin. with a 1 f capacitor at the c f pin, the typical drive frequency is 30 hz. this frequency can be raised, by decreasing the capacitor value, or lowered, by increasing the capacitor value. the rela- tionship between the capacitor value and the pwm fre- quency is linear. if a frequency of 15 hz is desired, a capacitor value of 2.0 f should be used. the fre- quency should be kept in the range of 15 hz to 35 hz. see section 7.2 for more details. 4.5 duty cycle control (v in and duty- cycle register) the duty cycle of the v out pwm drive signal can be controlled by either the v in analog input pin or by the duty-cycle register, which is accessible via the smbus interface. the control method is selectable via dutyc (bit 5<0>) of the configuration register. the default state is for v in control. if v in control is selected and the v in pin is open, the pwm duty cycle will default to 39.33%. the duty cycle control method can be changed at any time via the smbus interface. v in is an analog input pin. a voltage in the range of 1.62 v to 2.6 v (typical) at this pin commands a 30% to 100% duty cycle on the v out output, respectively. if the voltage at v in falls below the 1.62 v level, the duty cycle will not go below 30%. the relationship between the voltage at v in and the pwm duty cycle is shown in figure 4-5. figure 4-5: pwm duty cycle vs. v in voltage (typical). for the tc655 device, if the voltage at v in exceeds the 2.6 v (typical) level, an over temperature fault indica- tion will be given by asserting a low at the fault output and setting otf (bit 5 TC654/tc655 ds21734a-page 12 ? 2002 microchip technology inc. figure 4-6: ntc thermistor sensor network. the second method for controlling the duty cycle of the pwm output (v out ) is via the smbus interface. in order to control the pwm duty cycle via the smbus, dutyc (bit 5<0>) of the configuration register (register 6.3) must be set to a ? 1 ?. this tells the TC654/tc655 device that the duty cycle should be controlled by the duty cycle register. next, the duty cycle register must be programmed to the desired value. the duty cycle reg- ister is a 4 bit read/write register that allows duty cycles from 30% to 100% to be programmed. table 4-1 shows the binary codes for each possible duty cycle. table 4-1: duty-cycle register (duty-cycle) 4-bits, read/write this method of control allows for more sophisticated algorithms to be implemented by utilizing microcontrol- lers or microprocessors in the system. in this way, mul- tiple system temperatures can be taken into account for determining the necessary fan speed. as shown in table 4-1, the duty cycle has more of a step function look than did the v in control approach. because the step changes in duty cycle are small, they are rarely audibly noticeable, especially when the fans are integrated into the system. 4.6 pwm output (v out ) the v out pin is designed to drive two low cost npn transistors or n-channel mosfets as the low side power switching elements in the system as is shown in figure 4-7. these switching elements are used to turn the fans on and off at the pwm duty cycle commanded by the v out output. this output has complementary drive (pull up and pull down) and is optimized for driving npn transistors or n-channel mosfets (see section 2.0 for sink and source current capability of the v out drive stage). the external device needs to be chosen to fit the volt- age and current rating of the fan in a particular applica- tion (refer to section 7.5 output drive device selection). npn transistors are often a good choice for low current fans. if a npn transistor is chosen, a base current limiting resistor should be used. when using a mosfet as the switching element, it is sometimes a good idea to have a gate resistor to help slow down the turn on and turn off of the mosfet. as with any switch- ing waveform, fast rising and falling edges can sometimes lead to noise problems. as previously stated, the v out output will go to 100% duty cycle during power up and release from shutdown conditions. the v out output only shuts down when commanded to do so via the configuration register (sdm (bit 0<0>)). even when a locked rotor condition is detected, the v out output will continue to pulse at the programmed duty cycle. 4.7 sensing fan operation (sense1 & sense2) the TC654 and tc655 also feature microchip's propri- etary fansense technology. during normal fan opera- tion, commutation occurs as each pole of the fan is energized. the fan current pulses created by the fan commutation are sensed using low value current sense resistors in the ground return leg of the fan circuit. the voltage pulses across the sense resistor are then ac coupled through capacitors to the sense pins of the TC654/tc655 device. these pulses are utilized for cal- culating the rpm of the individual fans. the threshold voltage for the sense pins is 100 mv (typical). the peak of the voltage pulse at the sense pins must exceed the 100 mv (typical) threshold in order for the pulse to be counted in the fan rpm measurement. duty-cycle register (duty cycle) d(3) d(2) d(1) d(0) duty-cycle 000030% 0 0 0 1 34.67% 0 0 1 0 39.33% (default for v in open and when smbus is not selected) 001144% 0 1 0 0 48.67% 0 1 0 1 53.33% 011058% 0 1 1 1 62.67% 1 0 0 0 67.33% 100172% 1 0 1 0 76.67% 1 0 1 1 81.33% 110086% 1 1 0 1 90.67% 1 1 1 0 95.33% 1111100% v in +5 v ntc thermistor r 1 r 2 c 1 0.01 f 100 k ? @ 25c TC654/ tc655 gnd 34.8 k ? 14.7 k ? ? 2002 microchip technology inc. ds21734a-page 13 TC654/tc655 see section 7.4 for more details on selecting the appropriate current sense resistor and coupling capac- itor values. figure 4-7: fan current sensing. by selecting f1ppr (bits 2-1<01>) and f2ppr (bits 4- 3<01>) in the configuration register, the TC654 and tc655 can be programmed to calculate rpm data for fans with 1, 2, 4 or 8 current pulses per rotation. the default state assumes a fan with 2 pulses per rotation. the measured rpm data is then stored in the rpm- output1 (rpm1, for sense1 input) and rpm- output2 (rpm2, for sense2 input) registers. these registers are 9-bit read only registers which store rpm data with 25 rpm resolution. by setting res (bit 6<0>) of the configuration register to a ? 1 ?, the rpm data can be read with 25 rpm resolution. if this bit is left in the default state of ' 0 ', the rpm data will only be readable with resolution of 50 rpms, which represents 8-bit data. the maximum fan rpm reading is 12775 rpm. if this value is exceeded, counter overflow bits in the status register are set. r1co (bit 3<0>) and r2co (bit 4<0>) in the status register represent the rpm1 and rpm2 counter overflow bits for the rpm1 and rpm2 regis- ters, respectively. these bits will automatically be reset to zero if the fan rpm reading has been below the max- imum value of 12775 rpm for 2.4 seconds. see table 6-1 for rpm1, rpm2 and status register command byte assignments. 4.8 fan fault threshold and indication (fault ) for the TC654 and tc655 devices, a fault condition exists whenever a fan?s sensed rpm level falls below the user programmable threshold. the rpm threshold values for fan fault detection are set in the fan_fault1 and fan_fault2 registers (8-bit, read/ write). the rpm threshold represents the fan speed at which the TC654/tc655 devices w ill indicate a fan fault. this threshold can be set at lower levels to indicate fan locked rotor conditions or set to higher levels to give indications for predictive fan failure. it is recommended that the rpm threshold be at least 10% lower than the minimum fan speed which occurs at the lowest duty cycle set point. the default value for the fan rpm thresholds is 500 rpm. if the fan's sensed rpm is less than the fan fault threshold for 2.4 seconds (typical), a fan fault condition is indicated. when a fault condition, due to low fan rpm, occurs, a logic low is asserted at the fault output. f1f (bit 0<0>) and f2f (bit 1<0>) in the status register are set to ? 1 ? for respective low rpm levels on the sense1 and sense2 inputs. the fault output and the fault bits in the status register can be reset by setting ffclr (bit 7<0>) in the configuration register to a ? 1 ?. for the tc655 device, a fault condition is also indicated when an over temperature fault condition occurs. this condition occurs when the v out duty cycle exceeds the 100% value indicating that no additional cooling capability is available. for this condition, a logic low is asserted at the fault output and otf (bit 5 TC654/tc655 ds21734a-page 14 ? 2002 microchip technology inc. when the TC654/tc655 devices are brought out of a shutdown mode by resetting sdm (bit 0<0>) in the configuration register, all of the registers (except for the configuration and fan_fault1 & 2 registers) assume their default power up states. the configura- tion register and the fan_fault1 & 2 registers maintain the states they were in prior to the device being put into the shutdown mode. since these are the registers which control the parts operation, the part does not have to be reprogrammed for operation when it comes out of shutdown mode. 4.10 smbus interface (sclk & sda) the TC654/tc655 feature an industry-standard, 2-wire serial interface with factory-set addresses. by commu- nicating with the TC654/tc655 device registers, func- tions like pwm duty cycle, low power shutdown mode and fan rpm threshold can be controlled. critical infor- mation, such as fan fault, over temperature and fan rpm, can also be obtained via the device data regis- ters. the available data and control registers make the TC654/tc655 devices very flexible and easy to use. all of the available registers are detailed in section 6.0. 4.11 smbus slave address the slave address of the TC654/tc655 is 0011 011 and is fixed. this address is different from industry- standard digital temperature sensors (like tcn75) and, therefore, allow the TC654/tc655 to be utilized in sys- tems in conjunction with these components. please contact microchip technology inc. if alternate addresses are required. ? 2002 microchip technology inc. ds21734a-page 15 TC654/tc655 5.0 serial communication 5.1 smbus 2-wire interface the serial clock input (sclk) and the bi-directional data port (sda) form a 2-wire bi-directional serial port for communicating with the TC654/tc655. the follow- ing bus protocols have been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following serial bus conventions have been defined. table 5-1: TC654/tc655 serial bus conventions 5.1.1 data transfer the TC654/tc655 support a bi-directional 2-wire bus and data transmission protocol. the serial protocol sequencing is illustrated in figure 1-1. data transfers are initiated by a start condition (start), followed by a device address byte and one or more data bytes. the device address byte includes a read/write selection bit. each access must be terminated by a stop condi- tion (stop). a convention call acknowledge (ack) confirms the receipt of each byte. note that sda can only change during periods when sclk is low (sda changes while sclk is high are reserved for start and stop conditions). all bytes are transferred msb (most significant bit) first. 5.1.2 master/slave the device that sends data onto the bus is the transmit- ter and the device receiving data is the receiver. the bus is controlled by a master device which generates the serial clock (sclk), controls the bus access and generates the start and stop conditions. the TC654/tc655 always work as a slave device. both master and slave devices can operate as either trans- mitter or receiver, but the master device determines which mode is activated. 5.1.3 start condition (start) a high to low transition of the sda line while the clock (sclk) is high determines a start condition. all commands must be preceded by a start condition. 5.1.4 address byte immediately following the start condition, the host must transmit the address byte to the TC654/tc655. the 7-bit smbus address for the TC654/tc655 is 0011 011 . the 7-bit address transmitted in the serial bit stream must match for the TC654/tc655 to respond with an acknowledge (indicating the TC654/tc655 is on the bus and ready to accept data). the eighth bit in the address byte is a read-write bit. this bit is a ? 1 ? for a read operation or ? 0 ? for a write operation. during the first phase of any transfer, this bit will be set = 0 to indi- cate that the command byte is being written. 5.1.5 stop condition (stop) a low to high transition of the sda line while the clock (sclk) is high determines a stop condition. all operations must be ended with a stop condition. 5.1.6 data valid the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. term description transmitter the device sending data to the bus. receiver the device receiving data from the bus. master the device which controls the bus: ini- tiating transfers (start), generating the clock and terminating transfers (stop). slave the device addressed by the master. start a unique condition signaling the beginning of a transfer indicated by sda falling (high to low) while sclk is high. stop a unique condition signaling the end of a transfer indicated by sda rising (low to high) while sclk is high. ack a receiver acknowledges the receipt of each byte with this unique condi- tion. the receiver pulls sda low dur- ing sclk high of the ack clock-pulse. the master provides the clock pulse for the ack cycle. busy communication is not possible because the bus is in use. not busy when the bus is idle, both sda and sclk will remain high. data valid the state of sda must remain stable during the high period of sclk in order for a data bit to be considered valid. sda only changes state while sclk is low during normal data trans- fers. (see start and stop condi- tions) TC654/tc655 ds21734a-page 16 ? 2002 microchip technology inc. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is unlimited. 5.1.7 acknowledge (ack) each receiving device, when addressed, is obliged to generate an acknowledge bit after the reception of each byte. the master device must generate an extra clock pulse, which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. setup and hold times must be taken into account. during reads, a master device must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (TC654/tc655) will leave the data line high to enable the master device to generate the stop condition. 5.2 smbus protocols the TC654/tc655 devices communicate with three standard smbus protocols. these are the write byte, read byte and receive byte. the receive byte is a short- ened method for reading from, or writing to, a register which had been selected by the previous read or write command. these transmission protocols are shown in figures 5-1, 5-2 and 5-3. figure 5-1: smbus protocol: write byte format. figure 5-2: smbus protocol: read byte format. figure 5-3: smbus protocol: receive byte format. s address wr ack command ack data ack p 7 bits 8 bits 8 bits slave address command byte: selects which register you are writing to. data byte: data goes into the register set by the command byte. s address wr ack command ack 7 bits 8 bits slave address command byte: selects which register you are writing to. s address rd ack data nack p 7 bits 8 bits slave address: repeated due to change in data flow direction. data byte: reads from the register set by the command byte. s address rd ack data nack p 7 bits 8 bits slave address data byte: reads data from the register commanded by the last read byte or write byte transmission s = start condition p = stop condition shaded = slave transmission ack = acknowledge = 0 nack = not acknowledged = 1 wr = write = 0 rd = read = 1 ? 2002 microchip technology inc. ds21734a-page 17 TC654/tc655 6.0 register set the TC654/tc655 devices contain 9 registers that pro- vide a variety of data and functionality control to the outside system. these registers are listed below in table 6-1. of key importance is the command byte information, which is needed in the read and write pro- tocols in order to select the individual registers. table 6-1: command byte assignments 6.1 rpm-output1 & rpm-output2 registers (rpm1 & rpm2) as discussed in section 4.7, fan current pulses are detected at the sense1 and sense2 inputs of the TC654/tc655 device. the current pulse information is used to calculate the fan rpm. the fan rpm data for fans 1 & 2 is then written to registers rpm1 and rpm2, respectively. rpm1 and rpm2 are 9-bit registers that provide the rpm information in 50 rpm (8-bit) or 25 rpm (9-bit) increments. this is selected via res (bit 6<0>) in the configuration register, with ? 0 ? = 50 rpm and ? 1 ? = 25 rpm. the default state is zero (50 rpm). the maximum fan rpm value that can be read is 12775 rpm. if this value is exceeded, r2co (bit 4<0>) and r1co (bit 3<0>) in the status register will be set to a ' 1 ' to indicate that a counter overflow of the respec- tive rpm register has occurred. register 6-1 shows the rpm output register 9-bit format. register 6-1: rpm output registers (rpm1 & rpm2) register command read write por default state function rpm1 0000 0000 x? 0 0000 0000 rpm output 1 rpm2 0000 0001 x? 0 0000 0000 rpm output 2 fan_fault1 0000 0010 xx 0000 1010 fan fault 1 threshold fan_fault2 0000 0011 xx 0000 1010 fan fault 2 threshold config 0000 0100 xx 0000 1010 configuration status 0000 0101 x? 00x0 0x00 status. see section 6.4, status register explanation of x duty_cycle 0000 0110 xx 0000 0010 fan speed duty cycle mfr_id 0000 0111 x? 0101 0100 manufacturer identification ver_id 0000 1000 x? 0000 000x version identification: (x = ? 0 ? TC654, x = ? 1 ? tc655) d(8) d(7) d(6) d(5) d(4) d(3) d(2) d(1) d(0) rpm 0000000000 00000000125 00000001050 ......... ......... 11111111012750 11111111112775 TC654/tc655 ds21734a-page 18 ? 2002 microchip technology inc. 6.2 fan_fault1 & fan_fault2 threshold registers (fan_fault1 & fan_ fault2) the fan fault threshold registers (fan_fault1 and fan_ fault2) are used to set the fan fault threshold levels for fan 1 and fan 2, respectively. the fan fault registers are 8-bit, read/writable registers that allow the fan fault rpm threshold to be set in 50 rpm incre- ments. the default setting for both fan fault registers is 500 rpm ( 0000 1010 ). the maximum set point value is 12750 rpm. if the measured fan rpm (stored in rpm1 and rpm2 registers) drops below the value that is set in the fan fault registers for more than 2.4sec, a fan fault indication will be given. f1f (bit 0<0>) and f2f (bit 1<0>) in the status register indi- cate fan fault conditions for fan 1 and fan 2, respec- tively. the fault output will also be pulled low in a fan fault condition. changing ffclr (bit 7<0>) in the con- figuration register will reset the fan fault bits in the sta- tus register as well as the fault output. see register 6-2 for the fan fault threshold register 8-bit format. register 6-2: fan fault threshold registers (fan_fault1 & fan_fault2) d(7) d(6) d(5) d(4) d(3) d(2) d(1) d(0) rpm 000000000 0000000050 00000010100 ........ ........ 1111111012700 1111111112750 ? 2002 microchip technology inc. ds21734a-page 19 TC654/tc655 6.3 configuration register (config) the configuration register is an 8-bit read/writable multi-function control register. this register allows the user to clear fan faults, select rpm resolution, select v out duty cycle (fan speed) control method, select the fan current pulses per rotation for fans 1 & 2 (for fan rpm calculation) and put the TC654/tc655 device into a shutdown mode to save power consumption. see register 6-3 below for the configuration register bit descriptions. register 6-3: configuration register (config) r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 r/w-0 ffclr res dutyc f2ppr f2ppr f1ppr f1ppr sdm bit 7 bit 0 bit 7 ffclr: fan fault clear 1 = clear fan fault. this will reset the fan fault bits in the status register and the fault output. 0 = normal operation (default) bit 6 res: resolution selection for rpm output registers 1 = rpm output registers (rpm1 & rpm2) will be set for 25 rpm (9-bit) resolution. 0 = rpm output registers (rpm1 & rpm2) will be set for 50 rpm (8-bit) resolution. (default) bit 5 dutyc: duty-cycle control method 1 = the v out duty-cycle will be controlled via the smbus interface. the value for the v out duty-cycle will be taken from the duty-cycle register (duty_cycle). 0 = the v out duty-cycle will be controlled via the v in analog input pin. the v out duty-cycle value will be between 30% and 100% for v in values between 1.62 v and 2.6 v typical. if the v in pin is open when this mode is selected, the v out duty-cycle will default to 39.33%. (default) bit 4-3 f2ppr: fan 2 pulses per rotation the TC654/tc655 device uses this setting to understand how many current pulses per revolu- tion fan 2 should have. it then uses this as part of the calculation for the fan 2 rpm value in the rpm2 register. see section 7.7 for application information on determining your fan?s number of current pulses per revolution. 00 =1 01 = 2 (default) 10 =4 11 =8 bit 2-1 f1ppr: fan 1 pulses per rotation the TC654/tc655 device uses this setting to understand how many current pulses per revolu- tion fan 1 should have. it then uses this as part of the calculation for the fan 1 rpm value for the rpm1 register. see section 7.7 for application information on determining your fan?s number of current pulses per revolution. 00 =1 01 = 2 (default) 10 =4 11 =8 bit 0 sdm: shutdown mode 1 = shutdown mode. see section 4.9 for more information on low power shutdown mode. 0 = normal operation. (default) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown TC654/tc655 ds21734a-page 20 ? 2002 microchip technology inc. 6.4 status register (status) the status register provides all the information about what is going on within the TC654/tc655 devices. fan fault information, v in status, rpm counter overflow, and over temperature indication are all available in the status register. the status register is an 8-bit read only register with bits 6 and 7 unused. see register 6- 4 below for the bit descriptions. register 6-4: status register (status) u-0 u-0 r-x r-0 r-0 r-x r-0 r-0 ? ? otf r2co r1co vstat f2f f1f bit 7 bit 0 bit 7-6 unimplemented: read as ?0? bit 5 otf: over temperature fault condition for the TC654/tc655 device, this bit is set to the proper state immediately at startup and is therefore treated as an unknown (x). if v in is greater than the threshold required for 100% duty cycle on v out (2.6 v typical), then the bit will be set to a ? 1 ?. if it is less than the threshold, the bit will be set to ? 0 ?. this is determined at power-up. 1 = over temperature condition has occurred. 0 = normal operation. v in is less than 2.6 v. bit 4 r2co: rpm2 counter overflow 1 = fault condition. the maximum rpm reading of 12775 rpm in register rpm2 has been exceeded. this bit will automatically reset to zero when the rpm reading comes back into range. 0 = normal operation. rpm reading is within limits (default). bit 3 r1co: rpm1 counter overflow 1 = fault condition. the maximum rpm reading of 12775 rpm in register rpm1 has been exceeded. this bit will automatically reset to zero when the rpm reading comes back into range. 0 = normal operation. rpm reading is within limits (default). bit 2 vstat: v in input status for the TC654/tc655 devices, the v in pin status is checked immediately at power-up. if no external thermistor or voltage output network is connected (v in is open), this bit is set to a ? 1 ?. if an external network is detected, this bit is set to ? 0 ?. if the v in pin is open and smbus operation has not been selected in the configuration register, the v out duty cycle will default to 39.33%. 1 =v in is open. 0 = normal operation. voltage present at v in . bit 1 f2f: fan2 fault 1 = fault condition. the value for fan rpm in the rpm2 register has fallen below the value set in the fan_fault2 threshold register. the speed of fan 2 is too low and a fault con- dition is being indicated. the fault output will be pulled low at the same time. this fault bit can be cleared using the fan fault clear bit (ffclr (bit 7<0>)) in the configuration register. 0 = normal operation (default). bit 0 f1f: fan1 fault 1 = fault condition. the value for fan rpm in the rpm1 register has fallen below the value set in the fan_fault1 threshold register. the speed of fan 1 is too low and a fault con- dition is being indicated. the fault output will be pulled low at the same time. this fault bit can be cleared using the fan fault clear bit (ffclr (bit 7<0>)) in the configuration register. 0 = normal operation (default). legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2002 microchip technology inc. ds21734a-page 21 TC654/tc655 6.5 duty-cycle register (duty_cycle) the duty_cycle register is a 4-bit read/writable reg- ister used to control the duty cycle of the v out output. the controllable duty cycle range via this register is 30% to 100%, with programming steps of 4.67%.this method of duty cycle control is mainly used with the smbus interface. however, if the v in method of duty cycle control has been selected (or defaulted to), and the v in pin is open, the duty cycle will go to the default setting of this register, which is 0010 (39.33%). the duty cycle settings are shown in register 6-5. register 6-5: duty-cycle register (duty_cycle) 6.6 manufacturer?s identification register (mfr_id) this register allows the user to identify the manufac- turer of the part. the mfr_id register is an 8-bit read only register. see register 6-6 for the microchip manu- facturer id. register 6-6: manufacturer?s identification register (mfr_id) 6.7 version id register (ver_id) this register is used to indicate which version of the device is being used, either the TC654 or the tc655. this register is a simple 2-bit read only register. register 6-7: version id register (ver_id) d(3) d(2) d(1) d(0) duty-cycle 000030% 0 0 0 1 34.67% 0 0 1 0 39.33% (default for v in open and when smbus is not selected) 001144% 0 1 0 0 48.67% 0 1 0 1 53.33% 011058% 0 1 1 1 62.67% 1 0 0 0 67.33% 100172% 1 0 1 0 76.67% 1 0 1 1 81.33% 110086% 1 1 0 1 90.67% 1 1 1 0 95.33% 1111100% d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 01010100 d[1] d[0] version 00TC654 01tc655 TC654/tc655 ds21734a-page 22 ? 2002 microchip technology inc. 7.0 applications information 7.1 connecting to the smbus the smbus is an open collector bus, requiring pull-up resistors connected to the sda and sclk lines. this configuration is shown in figure 7-1. figure 7-1: pull-up resistors on smbus. the number of devices connected to the bus is limited only by the maximum rise and fall times of the sda and sclk lines. unlike i 2 c specifications, smbus does not specify a maximum bus capacitance value. rather, the smbus specification calls out that the max- imum current through the pull-up resistor be 350 a (minimum, 100 a, is also specified). therefore, the value of the pull-up resistors will vary depending on the system?s bias voltage, v dd . minimizing bus capaci- tance is still very important as it directly effects the rise and fall times of the sda and sclk lines. the range for pull-up resistor values for a 5 v system are shown in figure 7-1. although smbus specifications only require the sda and sclk lines to pull down 350 a, with a maximum voltage drop of 0.4 v, the TC654/tc655 has been designed to meet a maximum voltage drop of 0.4 v, with 3 ma of current. this allows lower values of pull- up resistors to be used, which will allow higher bus capacitance. if this is to be done, though, all devices on the bus must be able to meet the same pull down current requirements as well. a possible configuration using multiple devices on the smbus is shown in figure 7-2. figure 7-2: multiple devices on smbus. 7.2 setting the pwm frequency the pwm frequency of the v out output is set by the capacitor value attached to the c f pin. the pwm fre- quency will be 30 hz (typical) for a 1 f capacitor. the relationship between frequency and capacitor value is linear, making alternate frequency selections easy. as stated in previous sections, the pwm frequency should be kept in the range of 15 hz to 35 hz. this will eliminate the possibility of having audible frequencies when varying the duty cycle of the fan drive. a very important factor to consider when selecting the pwm frequency for the TC654/tc655 devices is the rpm rating of the selected fan and the minimum duty cycle that you will be operating at. for fans that have a full speed rating of 3000 rpm or less, it is desirable to use a lower pwm frequency. a lower pwm frequency allows for a longer time period to monitor the fan cur- rent pulses. the goal is to be able to monitor at least two fan current pulses during the on time of the v out output. example: your system design requirement is to oper- ate the fan at 50% duty cycle when ambient tempera- tures are below 20c. the fan full speed rpm rating is 3000 rpm and has four current pulses per rotation. at 50% duty cycle, the fan will be operating at approxi- mately 1500 rpm. equation if one fan revolution occurs in 40 msec, then each fan pulse occurs 10 msec apart. in order to detect two fan current pulses, the on time of the v out pulse must be at least 20 msec. with the duty cycle at 50%, the total period of one cycle must be at least 40 msec, which makes the pwm frequency 25 hz. for this example, a pwm frequency of 20 hz is recommended. this would define a c f capacitor value of 1.5 f. picmicro ? sda sclk v dd r r microcontroller TC654/tc655 range for r: 13.2 k ? to 46 k ? for v dd = 5.0 v sda sclk pic16f876 microcontroller tcn75 temperature sensor 24lc01 eeprom TC654/tc655 fan speed controller time for one revolution (msec.) 60 1000 1500 ----------------------- -40 == ? 2002 microchip technology inc. ds21734a-page 23 TC654/tc655 7.3 temperature sensor design as discussed in previous sections, the v in analog input has a range of 1.62 v to 2.6 v (typical), which repre- sents a duty cycle range on the v out output of 30% to 100%, respectively. the v in voltages can be thought of as representing temperatures. the 1.62 v level is the low temperature at which the system only requires 30% fan speed for proper cooling. the 2.6 v level is the high temperature, for which the system needs maximum cooling capability. therefore, the fan needs to be at 100% speed. one of the simplest ways of sensing temperature over a given range is to use a thermistor. by using an ntc thermistor as shown in figure 7-3, a temperature vari- ant voltage can be created. figure 7-3: temperature sensing circuit. figure 7-3 represents a temperature dependent volt- age divider circuit. r t is a conventional ntc thermistor, r 1 and r 2 are standard resistors. r 1 and r t form a par- allel resistor combination that will be referred to as r temp (r temp = r 1 * r t / r 1 + r t ). as the temperature increases, the value of r t decreases and the value of r temp will decrease with it. accordingly, the voltage at v in increases as temperature increases, giving the desired relationship for the v in input. the purpose of r 1 is to help linearize the response of the sensing net- work. figure 7-4 shows an example of this. there are many values that can be chosen for the ntc thermistor. there are also thermistors which have a lin- ear resistance instead of logarithmic, which can help to eliminate r 1 . if less current draw from v dd is desired, then a larger value thermistor should be chosen. the voltage at the v in pin can also be generated by a volt- age output temperature sensor device. the key is to get the desired v in voltage to system (or component) temperature relationship. the following equations apply to the circuit in figure 7-3. equation in order to solve for the values of r 1 and r 2 , the values for v in and the temperatures at which they are to occur need to be selected. the variables, t1 and t2, represent the selected temperatures. the value of the thermistor at these two temperatures can be found in the ther- mistor data sheet. with the values for the thermistor and the values for v in , you now have two equations from which the values for r 1 and r 2 can be found. example: the following design goals are desired: ? duty cycle = 50% (v in = 1.9 v) with temperature (t1) = 30c ? duty cycle = 100% (v in = 2.6 v) with tempera- ture (t2) = 60c using a 100 k ? thermistor (25c value), we look up the thermistor values at the desired temperatures: ?r t = 79428 ? @ 30c ?r t = 22593 ? @ 60c substituting these numbers into the given equations, we come up with the following numbers for r 1 and r 2 . ?r 1 = 34.8 k ? ?r 2 = 14.7 k ? figure 7-4: how thermistor resistance, v in , and r temp vary with temperature. figure 7-4 graphs three parameters versus tempera- ture. they are r t , r 1 in parallel with r t , and v in . as described earlier, you can see that the thermistor has a logarithmic resistance variation. when put in parallel with r 1 , though, the combined resistance becomes more linear, which is the desired effect. this gives us the linear looking curve for v in . r 2 r 1 r t i div v in v dd vt1 () v dd r 2 r temp t1 () r 2 + --------------------------------------- - = vt2 () v dd r 2 r temp t2 () r 2 + --------------------------------------- - = 0 20000 40000 60000 80000 100000 120000 140000 20 30 40 50 60 70 80 90 100 temperature (oc) network resistance ( ? ) 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 4.000 v in (v) ntc thermistor 100k @ 25oc v in voltage r temp TC654/tc655 ds21734a-page 24 ? 2002 microchip technology inc. 7.4 fansense network (r sense & c sense ) the network comprised of r sense and c sense allows the TC654/tc655 devices to detect commutation of the fan motor. r sense converts the fan current into a volt- age. c sense ac couples this voltage signal to the sense pins (sense1 & sense2). the goal of the sense network is to provide a voltage pulse to the sense pin that has a minimum amplitude of 120 mv. this will ensure that the current pulse caused by the fan commutation is recognized by the TC654/tc655 device. a 0.1 f ceramic capacitor is recommended for c sense . smaller values will require larger sense resis- tors be used. using a 0.1 f capacitor results in rea- sonable values for r sense . figure 7-5 illustrates a typical sense network. figure 7-5: typical sense network. the value of r sense will change with the current rating of the fan. a key point is that the current rating of the fan specified by the manufacturer may be a worst case rating. the actual current drawn by the fan may be lower than this rating. for the purposes of setting the value for r sense , the operating fan current should be measured. table 7-1 shows values of r sense according to the nominal operating current of the fan. the fan currents are average values. if the fan current falls between two of the values listed, use the higher resistor value. table 7-1: r sense vs. fan current figure 7-6 shows some typical waveforms for the fan current and the voltage at the sense pins. figure 7-6: typical fan current and sense pin waveforms. 7.5 output drive device selection the TC654/tc655 is designed to drive two external npn transistors or two external n-channel mosfets as the fan speed modulating elements. these two arrangements are shown in figure 7-7. for lower cur- rent fans, npn transistors are a very economical choice for the fan drive device. it is recommended that, for higher current fans (500 ma and above), mosfets be used as the fan drive device. table 7-2 provides some possible part numbers for use as the fan drive element. when using an npn transistor as the fan drive ele- ment, a base current limiting resistor must be used. this is shown in figure 7-7. when using mosfets as the fan drive element, it is very easy to turn the mosfets on and off at very high rates. because the gate capacitances of these small fan fan r iso1 r iso2 r sense2 r sense1 c sense2 c sense1 12 sense2 sense1 v out (0.1 f typical) (0.1 f typical) 715 ? 715 ? note: see table 7-1 for r sense1 and r sense2 values. r iso2 nominal fan current (ma) r sense (ohm) 50 9.1 100 4.7 150 3.0 200 2.4 250 2.0 300 1.8 350 1.5 400 1.3 450 1.2 500 1.0 ? 2002 microchip technology inc. ds21734a-page 25 TC654/tc655 mosfets are very low, the TC654/tc655 can charge and discharge them very quickly, leading to very fast edges. of key concern is the turn-off edge of the mos- fet. since the fan motor winding is essentially an inductor, once the mosfet is turned off, the current that was flowing through the motor wants to continue to flow. if the fan does not have internal clamp diodes around the windings of the motor, there is no path for this current to flow through, and the voltage at the drain of the mosfet may rise until the drain to source rating of the mosfet is exceeded. this will most likely cause the mosfet to go into avalanche mode. since there is very little energy in this occurrence, it will probably not fail the device, but it would be a long term reliability issue. the following is recommended: ? ask how the fan is designed. if the fan has clamp diodes internally, you will not experience this problem. if the fan does not have internal clamp diodes, it is a good idea to put one externally (figure 7-8). you can also put a resistor between v out and the gate of the mosfet, which will help slow down the turn-off and limit this condition. figure 7-7: output drive device configurations. table 7-2: fan drive device selection table (note 2) device package max vbe sat / vgs(v) min hfe vce/v ds fan current (ma) suggested rbase (ohms) mmbt2222a sot-23 1.2 50 40 150 800 mps2222a to-92 1.2 50 40 150 800 mps6602 to-92 1.2 50 40 500 301 si2302 sot-23 2.5 na 20 500 note 1 mgsf1n02e sot-23 2.5 na 20 500 note 1 si4410 so-8 4.5 na 30 1000 note 1 si2308 sot-23 4.5 na 60 500 note 1 note 1: a series gate resistor may be used in order to control the mosfet turn-on and turn-off times. 2: these drive devices are suggestions only. fan currents listed are for individual fans. q 1 gnd v dd r sense r base v out fan a) single bipolar transistor q 1 gnd v dd r sense v out b) n-channel mosfet fan TC654/tc655 ds21734a-page 26 ? 2002 microchip technology inc. figure 7-8: clamp diode for fan turn- off. 7.6 bias supply bypassing and noise filtering the bias supply (v dd ) for the TC654/tc655 devices should be bypassed with a 1 f ceramic capacitor. this capacitor will help supply the peak currents that are required to drive the base/gate of the external fan drive devices. as the v in pin controls the duty cycle in a linear fashion, any noise on this pin can cause duty cycle jittering. for this reason, the v in pin should be bypassed with a 0.01 f capacitor. in order to keep fan noise off of the TC654/tc655 device ground, individual ground returns for the TC654/ tc655 and the low side of the fan current sense resis- tor should be used. 7.7 determining current pulses per revolution of fans there are many different fan designs available in the marketplace today. the motor designs can vary and, along with it, the number of current pulses in one fan revolution. in order to correctly measure and commu- nicate the fan speed, the TC654/tc655 must be pro- grammed for the proper number of fan current pulses per revolution. this is done by setting the f2ppr and f1ppr bits in the configuration register to the proper values (see section 6.3 for settings). a fan's current pulses per revolution can be determined in the following manner. the first piece of information required is the fan's full speed rpm rating. the fan rpm rating can then be converted to give the time for one revolution using the following equation: equation the fan current can now be monitored over this time period. the number of pulses occurring in this time period is the fan's "current pulses per rotation" rating which is needed in order to accurately read fan rpm. example: the full speed fan rpm rating is 8200 rpm. from this, the time for one fan revolution is calculated to be 7.3 msec, using the previously discussed equa- tion. using a current probe, the fan current can be mon- itored as the fan is operating at full speed. figure 7-9 shows the fan current pulses for this example. the 7.44 msec window, marked by the cursors, is very near the 7.3 msec calculated above, and is within the toler- ance of the fan ratings. four current pulses occur within this 7.44 msec time frame. given this information, f2ppr (bits 4-3<01>) and f1ppr (bits 2-1<01>) in the configuration register, should be set to ' 10 ' to indicate 4 current pulses per revolution. figure 7-9: four current pulses per revolution fan. 7.8 how to eliminate false current pulse sensing during the pwm mode of operation, some fans will generate an extra current pulse. this pulse occurs when the external drive device is turned on and is, in most cases, caused by the fan's electronics that control the fan motor. this pulse does not represent true fan current and needs to be blanked out. this is particularly important for detecting a fan in a locked rotor condition. q 1 gnd r sense v out q1- n-channel mosfet fan time for one revolution (msec.) 60 1000 fan rpm ----------------------- - = ? 2002 microchip technology inc. ds21734a-page 27 TC654/tc655 figure 7-10 shows the voltage pulse at the sense pin, which is caused by the fan's "extra" current pulse during pwm output turn-on. figure 7-10: extra pulse at sense pin. this problem occurs mainly with fans that have a cur- rent waveshape like the one shown in figure 7-9. for configurations where an npn transistor is being used as the external drive device, the typical rsense and c sense scheme can continue to be used to sense the fan current pulses. in order to eliminate the extra cur- rent pulse, a slow down capacitor can be placed from the base of the transistor to ground. a 0.1 f capacitor is appropriate in most cases. this arrangement is shown in figure 7-11. this capacitor will help to slow down the turn-on edge of the transistor and reduce the amplitude of the extra current pulse. for configurations using an n-channel mosfet as the drive device, the slow down capacitor does not fix all conditions and the current sensing scheme must be changed. since the current for this type of fan always returns to zero, the coupling capacitor (c sense ) is not needed. instead, it will be replaced by an r-c configu- ration to eliminate the voltage pulse generated by the extra current pulse. this new sensing configuration is shown in figure 7-12. the values of the resistor/capac- itor combination should be adjusted so that the voltage pulse generated by the extra current pulse is smoothed and is not registered by the TC654/tc655 as a true fan current pulse. typical values for r slow and c slow are 1 k ? and 1000 pf, respectively. figure 7-11: transistor drive with c slow capacitor. figure 7-12: fet drive with r slow / c slow sense scheme. sense pin voltage "extra pulse" v out pwm fan fan r iso1 r iso2 c sense 12 (0.1 f typical) sense2 sense1 v out TC654/ tc655 (0.1 f typical) c slow1 (0.1uf gnd typical) (0.1 f typical) r sense2 c sense2 r sense1 c slow2 fan fan r slow2 r slow1 r sense2 r sense1 c slow1 1 2 (1000pf typical) sense2 sense1 v out TC654/ tc655 c slow 2 (1000pf typical) gnd (1 k ? typical) (1 k ? typical) TC654/tc655 ds21734a-page 28 ? 2002 microchip technology inc. 8.0 packaging information 8.1 package marking information * standard device marking consists of microchip part number, year code, week code, and traceability code. 10-pin msop device legend: 1 part number and temperature range 2 part number and temperature range 3 year and work week 4 lot id note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. 1 2 3 4 5 6 7 8 9 10 TC654e ywwnnn tc655e ? 2002 microchip technology inc. ds21734a-page 29 TC654/tc655 8.2 taping form 8.3 package information pin 1 component taping orientation for 10-pin msop devices w user direction of feed standard reel component orientation for tr suffix device p carrier tape, number of components per reel and reel size: package carrier width (w) pitch (p) part per full reel reel size 10-pin msop 12 mm 8 mm 2500 13 in. 10-pin msop .009 (0.23) .005 (0.13) .028 (0.70) .016 (0.40) .122 (3.10) .114 (2.90) .201 (5.10) .183 (4.65) .012 (0.30) .006 (0.15) pin 1 .006 (0.15) .002 (0.05) .020 (0.50) .122 (3.10) .114 (2.90) .043 (1.10) max. 6 max. dimensions: inches (mm) TC654/tc655 ds21734a-page 30 ? 2002 microchip technology inc. notes: ? 2002 microchip technology inc. ds21734a-page 31 TC654/tc655 systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ? device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products ? conferences for products, development systems, technical information and more ? listing of seminars and events 013001 TC654/tc655 ds21734a-page 32 ? 2002 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21734a TC654/tc655 2002 microchip technology inc. ds21734a-page33 TC654/tc655 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. x /xx package temperature range device device: TC654: pwm fan speed controller w/fault detection TC654t: pwm fan speed controller w/fault detection (tape and reel) tc655: pwm fan speed controller w/fault detection tc655t: pwm fan speed controller w/fault detection (tape and reel) temperature range: e = -40 c to +85 c package: un = plastic micro small outline (msop), 10-lead examples: a) TC654eun:: pwm fan speed controller w/fault detection b) TC654euntr: pwm fan speed controller w/fault detection (tape and reel) c) tc655eun: pwm fan speed controller w/fault detection d) tc655euntr: pwm fan speed controller w/fa ult de te ction (tape and reel) TC654/tc655 ds21734a-page 34 ? 2002 microchip technology inc. notes: ? 2002 microchip technology inc. ds21734a - page 35 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq , microid, mplab, pic, picmicro, picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, mxlab, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified. ds21734a-page 36 ? 2002 microchip technology inc. m americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-4338 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 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61-2-9868-6755 china - beijing microchip technology consulting (shanghai) co., ltd., beijing liaison office unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu microchip technology consulting (shanghai) co., ltd., chengdu liaison office rm. 2401, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou microchip technology consulting (shanghai) co., ltd., fuzhou liaison office unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - shanghai microchip technology consulting (shanghai) co., ltd. room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen microchip technology consulting (shanghai) co., ltd., shenzhen liaison office rm. 1315, 13/f, shenzhen kerry centre, renminnan lu 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